Current digital converter

General Description The AS processes via charge-balance method and converts lowest photocurrents at high accuracy. This product suits for the following applications: Metrology industrial and medical Process control Chemical analytics Infotainment monitors High-quality displays.

The ASdevices are mainly used for signal conditioning of sensors with current outputs. They are especially suitable for connection of photodiodes of array and row sensors. The possibility to adjust the transimpedance in 8 stages is a special feature. The adjustment is made by programming three pins and is valid for all channels together. It combines current-to-voltage TIA and analog-to-digital AD conversion, so that 4 separate current output devices e.

For each of the 4 inputs the AS provides an input amplifier with a track and hold circuit. The outputs of the track and hold stages are serial converted to bit digital words using an analog-to-digital converter ADC. Unlike switched capacitor circuits used in many ADCs, which require mixed-signal process variants with high-quality poly-poly or metal-metal capacitors, switched current DACs can make use of the standard CMOS processes. The designs have marched down the process generations from 0.

There are certain common features of these designs that have become givens. Because of this, it is important to note that many of the best circuit techniques are protected intellectual property and special care should be taken when developing a commercial product.

The data converter area is a mine field of patents. Almost universally, DACs with resolutions from 8 to 16 bits are split into two or more segments. The MSB segment is nearly always made from unit-weighted elements and is thermometer-coded. The number of bits in the MSB segment can vary from as few as 4 bits to as many as 8 bits, with 5 and 6 bits being the slightly more common choice.

The rest of the bits may be binary coded but are often further segmented into a thermometer-coded intermediate significant bit ISB section and a LSB binary-coded section. A notable exception to the use of thermometer coding is proposed in Ref. Here competitive performance is achieved using unit elements but combined and switched in binary fashion.

It also seems that P-channel metal oxide semiconductor PMOS currents and switches are used more often than N-channel metal oxide semiconductor NMOS currents, especially when the next circuit block in the signal chain does not reside on the same die as the DAC. Using PMOS devices on a standard twin-well process on P-type wafers provides the opportunity to isolate the back gates of the devices and bias them at some potential other than a power supply or ground.

Within a system with only positive power supplies, PMOS provides the convenience of having the output load referenced to ground as well. This example provides 14 bits of overall resolution. The five MSBs are composed of 31 unit-weighted elements and are thermometer-coded.

The remaining nine bits of the DAC are further segmented into four thermometer-decoded intermediate bits with the five LSBs being binary coded. Because just five of the MSBs are thermometer-coded, leaving 9 bits remaining, the inclusion of the thermometer coding for the 4 intermediate bits helps insure these 9 bits have sufficient INL and DNL accuracy for the overall resolution of the DAC.

The first comes from the digital logic and clock section and often directly scales with the sample frequency and the data pattern. CMOS has the advantage that the design will benefit from advances in process and supply voltage scaling. By way of illustration, the digital logic portion of DAC in Ref. A slightly more optimized logic block AQ2 of a low-power design in Ref.

At the same time, the CMOS logic can be operated from 1. The DAC in Ref. This lower power binary coding approach can be used when 10 bit performance levels are sufficient for the target application.

The second and third supply current categories are analog in nature. The full-scale output current is the major single contributor to the current in the analog supply. A popular output current for many designs is 20 mA because it provides 1 V signal swings in 50 ohm systems. An obvious place to trade-off power for signal amplitude is to lower the full-scale current.

The third part of the analog supply current is overhead and comes from the bandgap reference and various bias circuits. For example, with an analog supply overhead current of 5 mA in addition to the 20 mA full-scale output, the DAC in Ref.

Whereas a similar DAC in Ref. The addition of the cascode bias circuit increases the analog supply overhead current by 7 mA to a total of 12 mA. The challenge in power-efficient designs is to implement these performance-enhancing parts of the circuit while using a minimum of current. In the example from Ref. In some cases, this overhead current can be made to at least partially scale with the full-scale output. Designs such as these often make use of mixed voltage process options to allow the analog sections to be powered from higher supply voltages than the digital decoding logic and provide larger voltage swings on the output.

Device matching in CMOS processes has been studied and is well documented starting with the often cited work by Pelgrom in Ref.

By taking advantage of statistical averaging, layout techniques and random switching order, accuracy of up to 14 bits has been reported in Ref. The PMOS devices, which made up the main current sources in previous designs in 0.

An important aspect of design for good current source matching is the level of V gs - V T at which the devices operate. The larger this gate overdrive the less effect the random variations in V T have on the current sources.

With the available headroom a 5 V supply affords, it is possible to size the transistors with a generous V gs - V T of around mV in the 0. As the supply voltage shrinks such as in a 0.

For the DAC in Ref. It is also important to point out that the value of V T has scaled by mV in these examples going from the 0. It can be seen that the number of unit currents used for the MSB segment has a strong effect on the resulting linearity.

The use of statistical averaging across a large collection of smaller devices will result in improved matching performance. There are a number of approaches to how to arrange the current sources and the individual devices that compose them. Figure 7 shows one possible floor plan where each unit cell includes the output switch pair, current source, possibly with a cascode, along with the final re-timing latch and final decoding logic gate [2].

These unit cells are arranged in a two-dimensional array or matrix. The area required by the extra devices in each unit cell increases the distance between current source devices. This results in an accuracy disadvantage as we can see from Table 1. The two examples in Refs. Another issue with a matrix configuration such as this is that it forces distributing the final latch clock and the row, column data lines through cells, and may result in undesired coupling into the analog output and current-source bias nodes.

Another possible floor plan more or less used by the rest of the examples in Table 1 is shown in Figure 8. Here the circuit blocks are arranged by functional block. All the data latches and binary to thermometer decode logic are placed together in one block. The output switches are arranged in a single row with the analog currents entering on one side and the switch gate drive signals entering on the other.

By placing all the current source devices close together, the best matching can be achieved. Clock and data routing can be kept away from the analog output and current-source bias nodes.

The individual devices, which make up the unit current sources in the matrix, can be broken up and distributed around the matrix to cancel out process-induced gradients across the array. Figure 9a and 9b show two possible layout techniques to minimize matching errors in the current sources. The individual transistors, which make up each cell in the matrix, consists of two gate stripes sharing common source and drain diffusions, thus minimizing the overall area.

Often included, but not shown here, are rows of dummy devices around the periphery. This insures that the local environment is uniform when the polygates are patterned. In Figure 9a, the units are combined along diagonals of the matrix as proposed by Reynolds in Ref.

This is a simple interconnect method and requires the fewest number of metal layers because each combination of elements has at least two members on an edge and all interior cells are adjacent to another member of their group. In Figure 9b, the units are combined around a common centroid where the average distance from the center of the matrix is the same for all eight combinations. A number of minor variations on this basic concept have been proposed in Ref.

This is a more complex interconnect method and requires a larger number of metal layers. Many of the combinations are land locked so to speak with no members on an edge of the matrix. In order to insure optimal differential linearity the carry from an MSB to the sum of the remaining LSBs should be addressed. For low resolution LSB segments 4 to 5 bits individual transistors in the matrix could be combined in a binary fashion to generate the desired current values.

A current-splitting array of transistors sub-DAC can be used in place of a single cascode device as used in an MSB cell. For example, a 9 bit sub-DAC splitter could be further segmented into a 4 bit thermometer-coded upper segment and with binary-weighted elements for the five LSBs. The current splitter gate rail could be driven by a control loop separate from that of the MSB cascodes as shown in Figure 10 [28], closing the loop on the drain of the current source.

To achieve even higher accuracy or to increase yields with less layout area, trimming or calibration techniques are often used as in the literature [4,8,13,20,22]. There are two basic approaches to implementing self-calibration, foreground, and background. A converter, which is foreground-calibrated, must be taken off line and not used while being calibrated because as each current source is measured, it is removed from the output.

In background calibration, an additional current source is used to replace each current source as it is calibrated. This allows the DAC to be in use while being continuously calibrated.

However, the operation of removing and replacing current sources from the output could cause extra disturbances. The calibration clock may operate synchronous or asynchronous to the main DAC clock. There are also two basic approaches to storing the correction factors for the individual current sources. One technique, as proposed in Ref. In calibration mode, MN1 is diode connected through S2 and the gate will settle to a value such that the sum of Im and the current in MN1 will equal Iref.

In normal operation S1 switches the current to the output and switch S2 is opened holding the voltage on C gs , the gate of MN1. In the process of opening switch S2, a small error charge may be dumped onto C gs so care must be taken in how S2 is implemented. A dynamic technique such as this needs to be constantly refreshed and lends itself to background calibration. There is also a minimum clock rate requirement and the calibration will be lost if the clock is turned off during power saving modes.

There are certain systematic sources of error in this technique. The operating conditions of trim device MN1 and the devices in the main current source Im potentially vary between the calibration and normal operation modes.

However, while in normal operation Figure 11b , the V ds is set by whatever circuitry is connected to the terminal OUT. This could be a cascode device or the output switches of the DAC. Because of the finite output impedance of the current source devices, the current that results in the operating mode will be different than that flowing in the calibration configuration. Each cell is slightly different and the amount of adjustment needed, i. The change in current between calibration and operation modes will depend on the level of the adjustment.

This will limit the accuracy of the calibrated result. In order to maximize the headroom in designing current sources, the devices are often biased such that the V ds is marginally larger than the V dsat of the device.

Static storage of a digital correction value as used in Refs. In this approach, shown in Figure 12, the unit element to be calibrated, inside the dashed box, is measured against a master reference current and the difference adjusted as close to zero as possible through the successive approximation register SAR logic. The switches, which redirect the current either to the output node or the calibration hardware, act as the cascode devices and thus fix the drain voltage of the main current source device, MP1, to be the same, within the matching of the V gs of the two cascode switches, in both cases [27].

This can result in a much more accurate calibration. The additional circuitry used for the calibration is not clocked during normal operation and does not consume power or inject noise into the main signal path.

The calibration algorithm in its first cycle calibrates the master current from MP7 to be the same as MSB current segment number 1 with its calibration DAC set to mid-scale.

In the second cycle, MSB current number 1 is trimmed against the now adjusted master current. In the following cycles, the remaining MSB currents are adjusted in sequence to equal the master current. The configuration of the 6 bit calibration DAC is shown in Figure MP2 operates in the linear region and serves as a degeneration resistance for the devices in the splitting array.

These devices are weighted as shown totaling 63 units. Switches are configured to direct the currents to either the drain of MP1 increasing the output current of the cell or discarded to a return current node common to all calibration DACs. The voltage to which the discarded currents is returned is forced to be approximately equal to the drain of MP1 by a buffer amplifier, which is driven from the same cascode bias used in the cascode for MP1.

This insures that the splitting action is unaffected by how the switches are set. An INL mechanism that results from the use of a switched multiple current source architecture is code-dependent output impedance Figure 14a. As the number of current source elements is switched to the output, the resistance Rsw of that element's current source appears in parallel with the load resistor RL. As the number of elements turned on increases, the effective output impedance of the DAC in total decreases.

The varying impedance in parallel with the load resistor results in a nonlinear output voltage across the load. What we actually need to know is Rsw to design the DAC unit element. While it is true that switch output resistance requirements are greatly reduced for fully differential output configurations, as pointed out in Ref.

This maximizes the attenuation of the output swing seen at the common source nodes of the differential switches. The small signal attenuation of the switches is given by the ratio of the device gm to gds. Typical values of this ratio can be in the range of 20 to The parasitic capacitances shown in Figure 14b reduce the current source impedance as the output frequency increases [21]. As indicated in the figure, one or more cascode stages can be included to improve low-frequency output impedance, and extend the frequency range over which the current source output impedance is acceptable.

The simulated output impedance versus frequency for an example unit cell in a standard 0. The triangle curve is for the total of the drain to gate and drain to bulk junction capacitance of switches MP1 and MP2, which always appear on the output nodes independent of whether the switch is off or on. The other three curves are the impedance seen when the switch is on excluding the fixed drain capacitance.

The circle is for the case where the main current source devices connect directly to the switch pair. The square curve includes one cascode and the x curve includes two levels of cascode. For the two cascoded cases, the drain capacitance dominates the impedance until the DC resistance is reached.

We can use the same INL formula to gauge at what frequency the distortion will cross the required specification level. Again for differential output configurations, the even order distortion terms are greatly attenuated. At some point, the unavoidable nonlinearity of the drain to bulk junction capacitance will dominate. A switch. Tying the switch and cascode transistors' back gates to the supply reduces nonlinear capacitances, but for a large array, the total nonlinear capacitance can be significant.

The input of a unity-gain level shifting amplifier can be connected to the switch common source node and used to drive the back gate of the switches and cascode [4]. The nonlinear back gate capacitances now see the signal on both plates, thereby bootstrapping the well capacitances and leaving small linear parasitic capacitances.

The amplifier's dc level shift should set high to minimize the switch's nonlinear capacitance. The complexity and hardware of both double for each bit of resolution. In the ADC, the distribution of the analog input signal to the comparators with matched delays is much the same as the collection and combining of the individual unit current outputs of the DAC.

Also, as in the Flash ADC where the delays in the clock distribution to the individual comparators must be tightly matched, the clock distribution network driving the final stage of re-timing latches in the DAC is equally important.

One possible approach to this is propagation delay matching [4] illustrated in Figure 16a. Here if we assume that each cell has the same delay. Binary tree distribution structures are often used to match these delays as well as done in Ref. This results in a constant wavefront as illustrated in Figure 16b.

The clock distribution tree is arranged to have equal lengths from the driver to each cell. Likewise the output collection tree is arranged with equal length from each cell to the output pad s. The clock tree delay does not need to match the output tree delay. The physical placement of the unit cells in the layout is an important consideration and geometric shuffling of the placement is often used to breakup any linear gradients in the cell delay.

Figure 16 that might be present [33]. The observation was made in Ref. The U. This is accomplished by including a shadow or mirror data path with a one-to-one correspondence to the main data path. This shadow data path is driven by a data pattern is such a way that for each node in the main data path that does not change value at a given clock transition the corresponding node in the shadow path does.

Likewise, when a node in the main path does change the corresponding shadow node does not change. This makes the sum total of all nodes changing at each clock transition constant and independent of the data pattern. An example of this technique in an oversampled switched current audio DAC is proposed in Ref. In this approach, a dummy data shift register creates constant local digital edge activity on the supply, ground, and substrate.

The use of the dummy data to drive dummy switch devices balances the switching activity injected into the output stage thus minimizing the demodulation of out-of-band noise into the base band.

A similar notion, referred to as modified mismatch shaping MMS , is proposed in Ref. The idea is to set the number of elements or cells switching per clock period to a constant. An oversampling converter is assumed, where the maximum output bandwidth is reduced.

The choice of what fraction of the total number elements to set the constant to is problematic and the optimum is a function of the nature of the signals being converted, however. In any case, the constant can never be set to more than one-half the number of elements. This limits either the maximum amplitude or the maximum output frequency to only one-half of what it would have been otherwise.

Therefore, we conclude that, for a Nyquist rate converter, to make use of this constant element switching concept, we will need twice as many elements. As pointed out in the previous section, due to the mixed-signal nature of a DAC, digital data activity on the die will cause interference in the analog and clock sections of the device. This becomes an important performance issue as the output signal power is reduced or the frequency of the reconstructed output increases.

A special case of data pattern-dependent interference comes from the varying load seen by the final clock buffer, which drives the final rank of re-timing latches in the DAC [7]. The now popular six-transistor latch topology first used in Ref.

True and complements of the data are provided to inputs at D and DB and are allowed to change only when Clock is low, i. When the Clock signal transitions back to a low state, falling edge, and MN1,2 turn off, the state of Q and QB is held by the positive feedback around the weak inverters. An example of this effect is shown in Figure The effect is made more pronounced in this simulation for clarity by using a relatively weak clock buffer. The simulated time when the rising edge of the clock signal crosses mid supply, 1.

This simulation shows a 4 pSec difference between the x curve when the data does not change and the square curve when the data does change. Given the finite strength of the final clock buffer, the effect is magnified when a large number of latches are driven by the same common clock buffer and is proportional to the number of latches, which change their state.

In the case of thermometer-coded data, the number of unit MSB cells switching is proportional to the absolute value of the rate of change of the reconstructed output waveform. The time-shift of the output samples is thus proportional to this rate-of-change and so results in odd-order distortions, mainly third order. A strong clock buffer can be used, which minimizes the time differences thus the effect of the data-dependent clock loading is most prominent at high-output frequencies.

We can get a workable solution by taking the shadow or mirror data paths concept of Ref. One way this mirror data can be generated is shown in Figure 19 [29].

By doubling the number of latches, we have doubled the load on the clock driver, but it is now independent of the incoming data pattern. A more area-and power-efficient solution, which addresses this problem is shown in Figure 20 [8,30]. The bottom portion is the compensating load, which provides, through NMOS transistors MN3,4, a load that varies in a way opposite to the load provided by MN1,2.

The gate current that the buffer driving CLK needs to supply to transistor MN1 is a function of the relative voltage levels present at input D and output Q. If the voltage on D is the same as on Q a slightly smaller amount of charge is needed to turn on MN1 than if D is not equal to Q.

It can be seen that, for all possible combinations of the inputs and state of the latch, of the four switches MN1,2,3,4, the first will have high to low across source to drain S-D , the second will have low to high across S-D, the third will have high to high across S-D, and the fourth will have low to low across S-D. Therefore, as far as the charge that is needed to be supplied by the clock driver to turn on these four switches, it should be invariant with the data pattern.

It is necessary to balance the relative strengths of the weak inverters INV1,2, used in the latch, with the gated inverters INV5,6 to insure data-independent loading on the clock driver.

Gated inverters INV5,6 are sized such that their delay entering into tri-state is about the same as the regeneration time of the INV1,2 latch. This would be the lowest power solution. However, it is well known that for the best SFDR performance, the crossing point for the gate drive signals of the output current switch pair needs to be optimized [1,2].

The circuit that drives the differential switch should ensure that both switches are never completely off at the same time so that the current from the current source is always flowing at a constant value. This minimizes the excursion of the voltage on the switch common source node, Cs, during a transition.

Any current lost to parasitic capacitor C1 causes output distortions. The disturbance on Cs should be symmetric around the nominal DC value as indicated in Figure To the extent that the disturbance cannot be completely eliminated, as pointed out earlier, it is important that C1 be minimized [21]. This reduces any feed through of the gate drive signals to the outputs or the common source node. Another source of dynamic error relates back to the fact that a small attenuated amount of the output signal leaks through the gds of the differential switch onto node Cs.

Each switch element turns on at a different point in the transfer function and as a result will have a different wave shape on node Cs. In Figure 22b, we see what the signal on.

Cs will look like when a switch element is near the lower end of the transfer function. Similarly, for Figure 22c, we see the signal on Cs when a switch element is near the top of the transfer function. In Figure 20, note that the point at which MP1 and MP2 switch is determined by the crossing point of gate drive signals G1, G2 with respect to the value of node Cs.

If the relative value of Cs is modulated by the output swing and where in the transfer function the switch element is, the actual time point when the switches change will also be a function of the output swing and their position in the transfer function. This will result in a signal-dependent timing error seen in the output. As indicated in Figure 22b, MP1 switches from on to off when Cs is at its low point and MP1 switches from off to on when Cs is near the high point.

For the case shown in Figure 22c, just the opposite happens. Simulation results of an example case is shown in Figure 23, where the normalized zero crossing point of the differential output voltage at IA, IB is shown for three cases. The horizontal axis is 5 pSec per division and the vertical axis spans 1 mV. This could be a significant source of error when generating high-frequency outputs. The circuit, which produces the appropriate signals at the gates, is shown in Figure The output common mode level is most often ground but in this example circuit can be adjusted, external to the die, to accommodate interfacing to other circuits, which may require that the common mode voltage be as much as 1.

The amount of output shift can be traded off with increasing or decreasing the analog supply voltage. The VSB node is driven to a voltage approximately the V gs of the output switches above the output common mode level.